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Methods electromigration analysis conducting lines using the accelerated measurement test structures located in the wafer  

Authors
 Sivchenko A.S.
Date of publication
 2016

Abstract
 Increasing the amount of active and passive elements in the IC, increasing clock IC and densities in the current conducting all new tires dictate requirements metallization system and its reliability.
To provide predetermined characteristics IC transition from multilevel metallization on the basis of Al to multilevel metallization systems on the basis of using the elements Cu and new physicochemical properties as conductive bus. Complication metallization system requires the creation of operational tools of quality assessment and reliability at a stage of its production. Therefore, maintenance of the automated monitoring system to assess the reliability of the metallization is necessary to improve its quality and reduce the number of IC failures associated with failures in the metallization.
PURPOSE
The aim of this work is to develop techniques and automated monitoring software for electromigration analysis system IC metallization using accelerated measurement test structures located in the silicon wafer. This article is a continuation of [1] relating to quality control of production processes using the IC reliability test at wafer - WLR monitoring (Wafer Level Reliability Monitoring) [2].
METHODS
The main methods of test for resistance to electromigration can be divided into the test structures within the packaging (EM PLR) and test structures as part of the plate (EM WLR). EM PLR - electromigration tests are conducted in the packaging at a constant current and temperature [3]. The advantage of this test method is an independent change in the current and temperature of the test line, a low coefficient of acceleration of degradation that provides the best estimate of the operating time to failure. The disadvantage of it should be considered a high testing cost and long time measurement, and the measurement of copper metallization used in modern VLSI, measurement time, and all can be up to several months. These restrictions have contributed to the emergence of highly accelerated electromigration methods of measurement to which the WLR.
The main methods of WLR-test failures caused by electromigration, include: isothermal test - ISOT [4] and a standard test for the acceleration of electromigration in the structures on the wafer - SWET [5]. The main advantage of these methods is the high speed measurement and low test cost. The disadvantages include the inability to independent control of temperature and the current density at the time of measurement, as well as increased demands on the design of test structures at high acceleration degradation.
As a basis for the development of methodologies and automated measurement program we selected test method for resistance to electromigration based on isothermal test ISOT [4]. The advantage of this method is the high speed of measurement, relatively large coefficient of acceleration of degradation, the lack of strict requirements for the design of test structures and a good correlation of the results with the results of the test structures within the packaging (EM PLR). The algorithm consists of six parts:
The phase of determining the temperature coefficient of resistance TCR
Initialization phase
Temperature set phase and convergence
Phase stress test
Phase analysis of the measurement results
To implement 65 nm technology techniques developed and manufactured test crystals [7].
The test chip has a wide range of test structures for evaluating electromigration conductive tires made in various levels of the metal. Each test structure is focused on one dominant mechanism of physical failure. Design test structures designed with the ability to use accelerated measurement techniques and the use of Kelvin scheme for determining the resistance value.
To test the procedure in a language VEE Pro 9.0 is written testing program that allows you to assess the resistance of the conductive tires electromigration in an automatic measurement mode. [8] The program is designed for automated measurements of test structures composed of wafers by using Parametric meter Agilent B 1500 and a semi-automatic probe station SUSS PA 300.
The program allows you to define the parameters in the equation of Black on which to estimate the time to failure of the test patterns during normal operation.
Its distinguishing feature is the automated sequential measurements and data processing, which allows real-time to obtain the statistical distribution and, based on time, as you type the required number of measurements to calculate the parameters in the equation of Black. It also features a module for the preliminary measurement and mapping TCS plate on the type of failure. During measurement, the program generates an Excel file report measurements.
RESULTS
With the help of the developed technique measured the resistance to electromigration of conductive test lines carried out on 65 [nm] process technology in the first and second metals (M1 and M2). The test structures are arranged in a test chip, are long metal lines, and focused on the denial of a rupture or shorting conductor. Parameters structures M1/M2, respectively: the length of the test line 800/800 [um], the width of the test line of 0.09/0.1 [um], the thickness of the test line of 0.18/0.22 [um].
To calculate the activation energy Ea measured sample structures M1 and M2 at Tchuck =100 in the temperature range Ttest: 220, 250, 280 . Ea the activation energy values for structures M1/M2 amounted to 0.62/1.05 [eV]
To calculate the index of current density measured sample structures M1 and M2 at Ttest =250 in the temperature range Tchuck: 40, 70, 100 . The values of current density index n for structures M1/M2 amounted to 2.09/2.42.
DISCUSSION
The technique allows to quickly assess the degree of metallization reliability, conduct its certification, as well as improve the quality of metallization due to the development of new and optimization of existing technological processes of production.
In view of the results experiment can estimate the current density which provides the operating time to failure in 100,000 and 200,000 hours for the test structures M1 and M2 at 125 . For the structure of M1, it was 1,481 1,067 [/2] respectively, for the M2 structure 6,995 5,255 [/2].
Keywords
 electromigration, reliability, test structures, control of process parameters, MOSFET.
Library reference
 Sivchenko A.S. Methods electromigration analysis conducting lines using the accelerated measurement test structures located in the wafer // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2016. Proceedings / edited by A. Stempkovsky, Moscow, IPPM RAS, 2016. Part IV. P. 43-50.
URL of paper
 http://www.mes-conference.ru/data/year2016/pdf/D171.pdf

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