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A 14-bit 100 MS/s Pipelined ADC  

Authors
 Piatak I.M.
 Morozov D.V.
 Pilipko M.M.
Date of publication
 2016

Abstract
 A 14-bit 100 MS/s time-interleaved pipelined analog-to-digital converter (ADC) based on switched-capacitor circuits with digital error correction has been proposed. An analysis of the multiplying digital-to-analog converter (MDAC) of the 1.5-bit conversion stage has allowed to define required gain-bandwidth (GB) and DC gain characteristics of the op-amp, namely ΅0 = 85 dB and f1 = 600 MHz. Op-amp time-interleaving has been used to increase the conversion rate of the ADC up to 100 MS/s. A digital error correction algorithm has been proposed to compensate for gain and memory errors. It allowed to increase SNDR from 72 dB to 79 dB and SFDR from 75 dB to 87 dB. Reduction of capacitor values from the first to the following 1.5-bit conversion stages has made it possible to decrease power consumption of the pipeline ADC. The op-amp power consumption in the sample-and-hold circuit and in first 4 stages of the pipeline does not exceed 30 mW, in next 4 stages 20 mW, and in last 4 stages 10 mW.
A test chip of the pipeline ADC has been worked out based on simulation results for 180nm 1.8V CMOS technology of UMC Corporation. The total area of the chip is 2.5 mm x 1.1 mm. The differential input voltage range of the ADC is 1.6V. The energy efficiency figure of merit is no more than 0.37 pJ/c and ADC power consumption is no more than 270 mW. At the time being test chip measurements are done.
Keywords
 Pipelined ADC, time-interleaving, digital correction, 1.5 bit stage, operational amplifier, switched-capacitor circuits.
Library reference
 Piatak I.M., Morozov D.V., Pilipko M.M. A 14-bit 100 MS/s Pipelined ADC // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2016. Proceedings / edited by A. Stempkovsky, Moscow, IPPM RAS, 2016. Part 3. P. 73-78.
URL of paper
 http://www.mes-conference.ru/data/year2016/pdf/D164.pdf

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