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Algorithm for design rule violation clean-up after physical design  

 Talalay M.S.
 Ryzhenko N.V.
Date of publication

 This paper describes the approach for automated Design Rule Violation (DRV) clean-up of layout after placement, routing and metal fill physical design stages. After routing there are always empty regions in tracks that were not used to implement connections. Such empty regions violate design rules. Metal fill [1] is one of the final steps in physical design which aims to fill empty regions and to fix such violations. After this procedure new float or active fill wires can appear. Float or dummy wires are not connected to any device, active fill wires are the extensions of existing wires. The complexity and number of design rules only grows with each new tech node [2]-[3], and the metal fill process becomes more and more complicated. Routing and metal fill flows are separated: first routing is built, then metal fill is created. It leads to the fact that router can create theoretically unfillable topologies. To fix such places designer edits manually the routing topology near problem place, so that after that it will become fillable. Manual cleanup becomes a bottleneck in physical design. In this paper the automated solution is proposed.
The input of the flow is the Auto Place and Route (APR) block after routing and metal fill, with found DRVs. First, layout windows around problem places are cut from initial block; then tool automatically searches the minimal change in routing topology, so that it will become fillable on each window; and as the last step tool pushes back each fixed window to initial block. The locality of the problem places allow to apply SAT solver which is precise and rather popular today for layout tasks [3]-[11]. The main difference of the proposed approach in comparison to rerouting from scratch of the local areas is that tool builds minimal changes in existing routing topology. This property is important as it helps to mitigate the influence on electrical characteristics of the circuit. It is implemented through the sequence of SAT tasks formulated for discrete layout objects in rectangular local window. Design rules are modeled with Boolean expressions on discrete objects placed on routing grid [12]. In this paper the optimal way to represent such Boolean constraints is proposed to speed up significantly building and solving of SAT tasks for metal fill.
Experiments showed that in average 80% of DRVs can be fixed automatically, other DRVs are not localized and can be fixed only on block level. The solution is used for designing of new microelectronics at Intel Corporation.
 DRV clean-up, routing, metal fill, SAT solver.
Library reference
 Talalay M.S., Ryzhenko N.V. Algorithm for design rule violation clean-up after physical design // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2016. Proceedings / edited by A. Stempkovsky, Moscow, IPPM RAS, 2016. Part 1. P. 151-157.
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