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Elbrus-8C: the first Russian 28 nm 8-core processor  

Authors
 Kozhin A.S.
 Alfonso D.M.
 Demenko R.V.
 Kozhin E.S.
 Kolychev R.E.
 Kostenko V.O.
 Polyakov N.Y.
 Smirnova E.V.
 Smirnov D.A.
 Smolyanov P.A.
 Tikhorskiy V.V.
Date of publication
 2016

Abstract
 This paper is concerned with the first Russian 28 nm 8 core processor Elbrus¬ 8C developed by MCST company and released in 2015.
The goal of Elbrus 8C processor was to achieve more than 150 GFLOPS single-precision floating-point performance, making it around 3 times faster than its predecessor quad-core Elbrus 4C processor. Because of microprocessor performance depends on many of its subblocks any one of them can become a performance bottleneck. In order to meet the requirements the MCST’s team had to solve following design challenges:
• improve floating-point performance of each processor core,
• integrate 8 cores on a single chip doubling this number from previous generations,
• design high-bandwidth, low-latency scalable on-chip interconnect,
• augment cache hierarchy with new level of cache,
• increase memory and I/O subsystems bandwidth to feed the processor cores,
• develop an efficient cache coherence protocol for intra- and inter-processor communication,
• improve energy efficiency of a chip,
• increase reliability and die yield characteristics.
All these design challenges along with technological constraints on the processor area and power required complex and extensive changes of Elbrus ¬4C processor design taken as a reference point.
MCST’s flagship microprocessor Elbrus¬¬¬ 8C is an ASIC design implemented at 28 nm technology node. The 321 mm2 die contains 2.73 billion transistors. The target microprocessor’s clock frequency is 1.3 GHz. In this case the peak performance is 250 GFLOPS of single-precision (FP32) and 125 GFLOPS of double-precision (FP64).
In this paper, the microarchitecture, floorplan and key features of Elbrus ¬8C are introduced. The main technical decisions and technologies which enable to achieve high performance with area and power constraints are discussed.
Keywords
 Elbrus, core, multicore, cache hierarchy, memory subsystem, on-chip interconnect, coherency, ccNUMA.
Library reference
 Kozhin A.S., Alfonso D.M., Demenko R.V., Kozhin E.S., Kolychev R.E., Kostenko V.O., Polyakov N.Y., Smirnova E.V., Smirnov D.A., Smolyanov P.A., Tikhorskiy V.V. Elbrus-8C: the first Russian 28 nm 8-core processor // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2016. Proceedings / edited by A. Stempkovsky, Moscow, IPPM RAS, 2016. Part 2. P. 136-143.
URL of paper
 http://www.mes-conference.ru/data/year2016/pdf/D170.pdf

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