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Recurrent data-flow architecture: features and realization problems  

Authors
 Stepchenkov Yu.A.
 Diachenko Yu.G.
 Khilko D.V.
 Petrukhin V.S.
Date of publication
 2016

Abstract
 Results of development of the multi-core recurrent data-flow architecture (MRDA) focused on effective implementation of digital signal processing (DSP) algorithms are presented. Principal differences between MRDA and existing computer architectures are shown. Such differences make it possible to process the instructions in almost half the normal time using singular self-sufficient recurrently represented data-flow. One of the perspective approaches to building MRDA is presented in a form of a hybrid two-level architecture utilizing von Neumann control unit (NIOSII) and multi-core recurrent operational unit. Success of such solution has proven the effectiveness of data-flow paradigm in DSP and compatibility with existing computing environments.
Multiple non-recurrent mechanisms are shown to improve the performance of multiple DSP algorithms. Some of the mechanisms could be used in traditional DSP systems.
Another feature of MRDA is a perspective of self-timed implementation derived from the deep coherence between self-timed logic (data is ready) and self-timed hardware (results are ready). Currently despite synchronous design the interactions between functional blocks and instruction pipeline stages are asynchronous.
The future transition from synchronous FPGA-basis with NIOSII control unit towards custom-made KMOP-basis with KOMDIV control unit and a self-timed recurrent operational device in a form of a coprocessor is possible. Self-timed 64-bit division and square root unit as well as 64/32-bit MAC with rounding unit are already developed in a form of coprocessors.
Keywords
 data-flow architecture, recurrence, digital signal processing, match memory, superscalarity
Library reference
 Stepchenkov Yu.A., Diachenko Yu.G., Khilko D.V., Petrukhin V.S. Recurrent data-flow architecture: features and realization problems // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2016. Proceedings / edited by A. Stempkovsky, Moscow, IPPM RAS, 2016. Part 2. P. 120-127.
URL of paper
 http://www.mes-conference.ru/data/year2016/pdf/D182.pdf

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