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Converting VLSI macroblock structure by regrouping uniform function blocks  

 Safyannikov N.M.
 Frolkin A.K.
Date of publication

 The article is devoted to structure optimization of repeating VLSI macroblocks. Two ways are considered, the techniques change structure-layout design that allow to reduce layout square and sometimes increase speed result yield.
One important requirement for VLSI projects is high elements density on chip layout. The highest elements density on chip provided by collection of transistors with complex shape and with different orientation in space. One more method is optimizing cells placement and routing between cells. In spite of some algorithms of library cells placement and routing are already existed, those algorithms do not provide optimum results because results depend on cells quality.
The first optimization technique is regrouping structural-layout scheme. The main idea is to divide macroblock into functional blocks and try some different versions of blocks placement or shape. Pipelined multiplier is the example represented in the article. It was divided into blocks, then some blocks were moved and rotated. The operation allows to reduce layout square.
The second technique is transfer part of function out the considered section. The technique means changing device function and device layout. For example transfer of synchronization registers subsection out pipelined arithmetic multiplier allows to get partial product before full result is computed. This technique reduces layout squire if one functional section is used by some macroblocks and also the technique increases a speed in mode where lower bits are enough.
 VLSI macroblocks, layout technique, multiplier.
Library reference
 Safyannikov N.M., Frolkin A.K. Converting VLSI macroblock structure by regrouping uniform function blocks // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2016. Proceedings / edited by A. Stempkovsky, Moscow, IPPM RAS, 2016. Part 3. P. 226-231.
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