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Decompilation of Flat CMOS Circuits in SPICE Format 
 


Authors 
 Cheremisinov D.I. 
 Cheremisinova L.D. 
Date of publication 
 2018 
DOI 
 10.31114/207877072018128 

Abstract 
 This paper presents a computer program for automatically extracting the hierarchy of a largescale digital CMOS circuit from its transistorlevel netlist. By analogy with programming, the process of conversion of a flat CMOS circuit in SPICE format to a hierarchical circuit in the same format is referred as decompilation. Automatic recognition of a highlevel structure from the transistor level netlist of a circuit is important for many tasks in VLSI circuit design.
In the SPICE format, electrical circuits consist of elements that are connected to each other by nets, and the natural formal model for describing the circuit is a colored undirected bipartite graph. One part is made up of the terminals of the elements and the ports of the circuit, and the other is the connection between the terminals, i.e. nets.
The decompilation is a factoring of flat netlist. If we don’t known how recognize a factor as subcircuit, then the decompilation problem is not tractable. Every group of transistors can be refactored as subcircuit. We select as subcircuit the group of the transistorfor, which it is possible to define a logic function.
Our program perform the following sequence of steps: 1) analyze the original SPICE description and construct a hash table for storing the bipartite color graph of the circuit, 2) divide the bipartite color graph into channelconnectedcomponents (CCC), recognize the correct CCC, find their logical function in the form of an algebraic formula and construct a hash table for storing instances of CMOS gates, 3) generate a hierarchical SPICE description.
Structural analysis of digital circuits was broadly covered by research in the past. For the recognition of subcircuit two classes of approaches exist: library based approaches and algorithmic approaches. Library based approaches use library circuits as templates for recognition of subcircuits and their recognition ability is limited to subcircuits contained in the library. Algorithmic approaches recognize subcircuits for which haves the possibility for to compute the logic function of the gate. Our method allows us to recognize subcircuits with the same logic functions that are not isomorphic at the transistor level. 
Keywords 
 VLSI design, transistorlevel netlist, CMOS circuits redesign, SPICE format, subcircuit recognition, algebraic factorization of DNF, canonization of colored undirected graphs. 
Library reference 
 Cheremisinov D.I., Cheremisinova L.D. Decompilation of Flat CMOS Circuits in SPICE Format // Problems of Perspective Micro and Nanoelectronic Systems Development  2018. Issue 1. P. 28. 
URL of paper 
 http://www.mesconference.ru/data/year2018/pdf/D006.pdf 

