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Analysis Based on TCAD Simulation of Failure Tolerance of the Elements on the Cells STG DICE for 65-nm CMOS Blocks of Associative Memory  

Authors
 Katunin Yu.V.
 Stenin V.Ya.
Date of publication
 2018
DOI
 10.31114/2078-7707-2018-4-182-189

Abstract
 The paper presents the TCAD simulation of the 65-nm bulk CMOS logical element of matching, and element of masking on base STG DICE cell with the combinational logic. These items are for the content addressable memory (associative memory) and the translation lookaside buffers for 65-nm CMOS bulk technology. The combinational logic consists of two tristate inverters (for elements of matching) and additionally consists of two normal inverters (for elements of masking). The STG DICE cell (Spaced Transistor Groups DICE) is different from the standard DICE (Double Interlocked Cell) in that the transistors are separated into two special groups. That is why the charge collection with the track of single nuclear particles impacted on one of these groups does not lead to upset logical state of this memory cell. Failure tolerance of the elements of matching and elements of masking based on the STG DICE cell increases by the separation of its transistors (including the combination logic) into two blocks. Each block consists of the one group of transistors of the STG DICE cell and transistors of the one of two tristate inverters (for elements of matching) and two additional normal inverters moreover (for elements of masking). The charge collection with tracks of nuclear particles was modelling using tracks along the normal to the chip surface. Linear energy transfers on tracks were in range 10-60 MeV×cm2/mg. The charge collection with tracks onto the linear energy transfer up to 60 MeV×cm2/mg are not upsets data in STG DICE cells with tracks along the normal to the chip surface. In the combinational logic can be noise pulses up to 0.6 ns in the range of the energy transfer 30-60 MeV×cm2/mg. The effects of single-event transients under impacts of single nuclear particles on CMOS combinational logical elements are minimized by separation transistors into special groups and the co-location in the each group the compensation transistors together with the transistors, which can be affected by single nuclear particle. The combinational logical elements with the proposed layout of the topological single-event compensation designed for the blocks of matching of the translation lookaside buffers and the associative memories.
Keywords
 logical element, simulation, error impulse correction, nuclear particle, failure tolerance, track, memory cell.
Library reference
 Katunin Yu.V., Stenin V.Ya. Analysis Based on TCAD Simulation of Failure Tolerance of the Elements on the Cells STG DICE for 65-nm CMOS Blocks of Associative Memory // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2018. Issue 4. P. 182-189.
URL of paper
 http://www.mes-conference.ru/data/year2018/pdf/D015.pdf

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