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Circuit Design of Synchronizing Devices Within High-speed Data Services  

 Makarevich A.L.
 Sokovnich S.M.
 Tokar M.S.
Date of publication

 The correctness of the information transmitted by information and communications systems and networks is largely determined by the quality of the synchronization system. The optimal circuit design for the construction of synchronizing devices and the entire system for maintaining synchronous operation, in this case, is of a crucial significance. In the research, we analyze and summarize the results of circuit simulation for several variants of the construction of synchronizing devices components, implemented within the framework of classical CMOS technology and circuit technology. The implementation of the proposed solutions on CMOS transistors with submicron design rules will require only the usage of new transistor models, which parameters are determined by a group of technological operations of their manufacturing process and inherent structural and technological limitations. This article describes methods of designing PLL components using SPICE models for CMOS transistors with design standards 1 2 m (the model proposed by us) and 90 45 nm from Microwind. We propose classic circuit solutions to implement PLL components on bidirectional switches and inverters. The model from Microwind was supplemented by some important parameters. This made it possible to obtain simulation results close to real and well consistent with literature data.
 phase-lock-loop frequency control (PLL), PLL components, phase-lock detector (comparer), SPICE models of PLL components, signal transmission, synchronization, timing extraction.
Library reference
 Makarevich A.L., Sokovnich S.M., Tokar M.S. Circuit Design of Synchronizing Devices Within High-speed Data Services // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2018. Issue 1. P. 147-151.
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