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A 4-channel Multi-standard Adaptive Serial Transceiver for the Range 1.25-10.3Gb/s in CMOS 65nm  

Authors
 Larionov A.V.
 Buyakova O.N.
 Sysoeva O.V.
 Osina S.E.
 Zadiabin S.O.
 Aleksan P.A.
 Tarasov I.V.
 Rogatkin Yu.B.
 Masterov V.
Date of publication
 2018
DOI
 10.31114/2078-7707-2018-2-115-122

Abstract
 The article presents a fully adaptive serial 4-channel transceiver for the standards 10G Base-R, SATA, PCI Express, FC, RapidIO, DisplayPort. The unit is capable of operating in the range 1.25÷10.3125Gb/s with a bit error rate less 10-12. The total jitter of the output signal transmitter <26ps@10.3125Gb/s for BER=10-12. At 10.3125Gb/s receiver tolerance to high-frequency jitter >0.3UI (30% of the unit interval) with channel loss 24dB for polynomial PRBS31. The transceiver demonstrates error-free data processing at a speed 10.3125Gb/s for a channel with a total attenuation of 33dB. The unit is designed using CMOS 65nm technology and has power consumption of 760mW@10.3125Gb/s. The features of this transceiver include: 1) the decision feedback equalizer with direct access with reduced power consumption, 2) the controller for searching for the optimum position of the auxiliary clock phase to increase the receiver's tolerance, 3) the pseudo-differential cascode output buffer, 4) the controller of the minimally admissible differential voltage of the output buffer
Keywords
 equalizer, decision-feedback equalizer, receiver, transceiver, DFE, direct-feedback architecture, active inductor, CML, SSLMS, sign-sign least mean square.
Library reference
 Larionov A.V., Buyakova O.N., Sysoeva O.V., Osina S.E., Zadiabin S.O., Aleksan P.A., Tarasov I.V., Rogatkin Yu.B., Masterov V. A 4-channel Multi-standard Adaptive Serial Transceiver for the Range 1.25-10.3Gb/s in CMOS 65nm // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2018. Issue 2. P. 115-122.
URL of paper
 http://www.mes-conference.ru/data/year2018/pdf/D041.pdf

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