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Optimization of TSMC 28nm Physical and Logical VLSI Design Flow  

 Vlasov A.O.
 Gorelov A.A.
 Emin E.K.
Date of publication

 The article reveals the problems of analysis of parasitic delays at all stages of the RTL-to-GDS design flow. As a result, recommendations for performing logical and physical design flows for the technological process TSMC 28nm HPC+ have been formed.
As feature size standards decrease, the number of problems related to the optimization and performing of VLSI development flows have been increased.
As the main problems it is possible to allocate:
1. Increasing the role of parasitic delays for the overall project's speed
2. The problem of increasing static power consumption
3. Increasing the number of required conditions for effective design analysis
4. Increasing the number of functional cells options, which creates the problem of choosing the optimal set of library elements for design
In this article, as an example of application above-mentioned problems we used the high-performance block the microprocessor core of the KOMDIV 64 series developed by the SRISA. Performance of this block is as critical as power consumption. Analysis of the results of logical and physical synthesis flows was performed considering the most critical parameters such as performance and static power consumption. The whole flow of integral circuit development has been carried out using CADENCE software. Logic synthesis has been performed in EDA GENUS, physical – EDA INNOVUS.
EDA Genus offers two modes of logical synthesis: synthesis with physical layout estimation (PLE) and synthesis with topographical estimation. Parasitic parameter and topological location of interface input/output ports, memory elements, custom blocks. The results obtained in each of the modes allowed us to suggest a number of recommendations for the logical design flow. Also the optimization of design critical parameters was performed with the TSMC_28nm HPC+ technology special features.
Also as a part of physical synthesis an optimal set of the PVT implementation corners was considered. Taking into account 9 PVT implementation corners and 5 different models of the parasitic parameters extraction, there are 45 different design variations depending on operating conditions and technological manufacturing. Data analysis allowed us to acquire a set of 5 of the most critical implementation corners. This set was applied in the design during MMMC design flow. As a result we obtained block variation with the most optimal parameters, fully meeting the terms of reference in all required conditions.
 TSMC 28nm HPC+, Genus, logical synthesis, Innovus, physical synthesis.
Library reference
 Vlasov A.O., Gorelov A.A., Emin E.K. Optimization of TSMC 28nm Physical and Logical VLSI Design Flow // Problems of Perspective Micro- and Nanoelectronic Systems Development - 2018. Issue 1. P. 38-44.
URL of paper

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